1. Field of the Invention
The present invention relates to a plasma display device in which a plasma display panel is used.
2. Description of the Related Art
For driving a plasma display panel (PDP), a one-field display period is composed of a plurality of sub-fields, each including an addressing period and a sustain period, to display images at multiple gradation levels. In a gradation display method, when the number of display lines is increased for a higher definition or when the number of sub-fields is increased for an increased number of gradation levels, the proportion of the addressing period relatively increases in the one-field display period. If the pulse width of a scanning pulse is simply narrowed down to limit the increased addressing period, a selective discharge becomes uncertain due to a delayed discharge and the like. To solve this problem, a driving method, which divides column electrodes of a PDP into two groups, i.e., an upper and a lower region of the panel and permits simultaneous address scanning in the upper and lower regions of the panel to reduce the addressing period to one half, is employed. The field is used herein in consideration of an interlace video signal such as a video signal of the NTSC standard, and corresponds to a frame in a non-interlace video signal.
FIG. 1 generally shows a configuration of a plasma display device to which the conventional driving method is applied. The plasma display device comprises a PDP 100, a driving control circuit 101, an X-row electrode driving circuit 102, a Y-row electrode driving circuit 103, an upper column electrode driving circuit 104, and a lower column electrode driving circuit 105. The PDP 100 comprises column electrodes Du1-Dum and column electrodes Dd1-Ddm as address electrodes, and row electrodes X1-Xn and row electrodes Y1-Yn which are arranged to intersect with these column electrodes. The column electrodes Du1-Dum are column electrodes in an upper region of the panel, and intersect with row electrodes X1-Xn/2 and row electrodes Y1-Yn/2. The column electrodes Dd1-Ddm are column electrodes in a lower region of the panel, and intersect with row electrodes Xn/2+1-Xn and row electrodes Yn/2+1-Yn. Row electrode pairs (X1, Y1), (X2, Y2), (X3, Y3), . . . , (Xn, Yn) serve as a first display line to an n-th display line on the PDP 100, respectively. At an intersection of each of the display lines and each of the column electrodes Du1-Dum and column electrode Dd1-Ddm, a display cell CS is formed to serve as a pixel.
The driving control circuit 101 generates control signals to the respective X-row electrode driving circuit 102, Y-row electrode driving circuit 103, upper column electrode driving circuit 104, and lower column electrode driving circuit 105 in response to an input video signal in accordance with the sub-field method mentioned above.
FIG. 2 shows a light emission driving sequence in accordance with the sub-field method. In this light emission driving sequence, in a display period for each field (frame) of an input video signal, i.e., in a unit display period which is spent for displaying one screen of image, N sub-fields SF1-SFN are executed. Each of the sub-fields SF1-SFN includes an addressing stage W, a sustain stage I, and an erasure stage E. Only the first sub-field SF1 includes a reset stage R. These sub-fields SF1-SFN are weighted for the luminance in an ascending order in each field. Specifically, the first sub-field SF1 has the smallest luminance weighting coefficient, and the last sub-field SFN has the largest luminance weighting coefficient. A scanning pulse in the addressing stage W is first applied to the row electrode Y1 in the upper region of the panel, and sequentially applied to the row electrodes Y2, Y3, . . . , Yn/2 in that order. Simultaneously with the application, the scanning pulse is applied to the row electrode Yn in the lower region of the panel, and sequentially applied to the row electrodes Yn−1, Yn−2, . . . , Yn/2+1 in that order.
The X-row electrode driving circuit 102 applies a variety of driving pulses to each of the row electrodes X1-Xn of the PDP 100 in response to a control signal supplied from the driving control circuit 101. The Y-row electrode driving circuit 103 applies a variety of driving pulses to each of the row electrodes Y1-Yn of the PDP 100 in response to a control signal supplied from the driving control circuit 101. The upper column electrode driving circuit 104 applies a pixel data pulse to the column electrodes Du1-Dum of the PDP 100 in response to a control signal supplied from the driving control circuit 101. The lower column electrode driving circuit 105 applies a pixel data pulse to the column electrode Dd1-Ddm of the PDP 100 in response to a control signal supplied from the driving control circuit 101.
FIG. 3 is a diagram showing timings at which a variety of driving pulses are applied to the column electrodes D, row-electrodes X1-Xn and Y in the sub-field SF1 extracted from the sub-fields SF1-SFN.
First, in a reset stage R executed only in the first sub-field SF1, the X-row electrode driving circuit 102 simultaneously applies a reset pulse RPX of negative polarity, as shown in FIG. 3, to the row electrodes X1-Xn. Further, simultaneously with the application of the reset pulse RPX, the Y-row electrode driving circuit 103 simultaneously applies the row electrodes Y1-Yn with a first reset pulse RPY1 of positive polarity which has the pulse waveform, the voltage value of which slowly increases over time to reach a peak voltage value, as shown in FIG. 3. With the simultaneous application of the reset pulse RPY1 and reset pulse RPX of negative polarity, a first reset discharge is produced between the X-row electrode and Y-row electrode in each of all the display cells. After the end of the first reset discharge, a predetermined amount of wall charge is formed in a discharge space of each display cell. Subsequently, the Y-row electrode driving circuit 103 generates a second reset pulse RPY2 of negative polarity which changes slow in voltage at a falling edge, and simultaneously applies the second reset pulse RPY2 to all the row electrodes Y1-Yn. In response to the application of the second reset pulse RPY2, a second reset discharge is produced between the X-row electrode and the Y-row electrode in each of all the display cells. The second reset discharge extinguishes the wall charge formed in each of all the display cells.
Next, in the addressing stage W of each sub-field, each of the upper column electrode driving circuit 104 and lower column electrode driving circuit 105 generates a pixel data pulse for setting whether or not each discharge cell should be driven to emit light in the sub-field based on an input video signal. The upper column electrode driving circuit 104 sequentially applies the pixel data pulse for one display line (m) to the column electrodes Du1-Dum as a group of pixel data pulses DP1, DP2, . . . , DPn/2. The lower column electrode driving circuit 105 sequentially applies th pixel data pulse for one display line to the column electrodes Dd1-Ddm as a group of pixel data pulses DPn, DPn−1, . . . , DPn/2+1. In the meantime, the Y-row electrode driving circuit 103 sequentially applies a scanning pulse of negative polarity to the row electrodes Y1-Yn/2 in synchronism with the timing of each of the pixel data pulses DP1-DPn/2, and sequentially applies the scanning pulse SP of negative polarity to the row electrodes Y1-Yn/2+1 in synchronism with the timing of each of the pixel data pulses DPn-DPn/2+1. In this event, a discharge (selective discharge) is produced only in those display cells which are applied with the scanning pulse SP and is also applied with the pixel data pulse at high voltage, resulting in the formation of a predetermined amount of wall charge in the discharge space of each of these display cells. With the execution of the addressing stage W, each discharge cell is set to one of a lit cell state in which a predetermined amount of wall charge exists, and an unlit cell state in which no wall charge exists.
Next, in the sustain stage I of each sub-field, each of the X-row electrode driving circuit 102 and Y-row electrode driving circuit 103 applies sustain pulses IPX, IPY of positive polarity to the row electrodes X1-Xn, Y1-Yn a number of times (for a duration) corresponding to the luminance weighting of the sub-field. In the sustain stage I of each of the sub-fields SF1-SF(N), only those discharge cells which are in the lit cell state as mentioned above discharge for sustaining the light each time they are applied with the sustain pulse IPX or IPY.
Then, in the erasure stage E of each sub-field, the Y-row electrode driving circuit 103 sequentially applies the row electrodes Y1-Yn with an erasure pulse EP of negative polarity as shown in FIG. 3. In response to the application of the erasure pulse EP, an erasure discharge is produced in those discharge cells which have produced the sustain discharge in the preceding sustain stage I. The erasure discharge extinguishes the wall charges formed in the display cells, causing the discharge cells to transition to the unlit cell state.
However, in the conventional plasma display device, the address scanning is sequentially performed toward a display line which adjoins a boundary from which the column electrodes are divided from a display line at the upper end and a display line at the lower end of the panel. This address scanning technique requires a column electrode driving circuit for each of the column electrode groups which are divided into an upper and a lower section, resulting in a higher cost. Also, a problem still remains unchanged in regard to the stability of the address discharge because the address discharge is more difficult to occur in display lines which are scanned in later turns, as compared with the display line which is scanned first.